Veröffentlichungen

2021

A. Klemd, P. Nowak, P. Benois, E. Gerat, B. Klauer, U. Zölzer
Exponential Sine Sweep Measurement Implementation Targeting FPGA Platforms
International Conference on Field-Programmable Technology (FPT`21); Conference

C. Sander, D. Meyer, B. Klauer
A Survey of C++ based Agent Software Frameworks
International Conference on Electrical, Computer and Energy Technologies (ICECET`21); Conference

A. Klemd, J. Timmermann, B. Klauer, D. Sachau
A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
International Conference on Field-Programmable Logic and Applications (FPL`21); Conference

M. Eckert, J. Krooß, B. Klauer, A. Fay F. Kümmerlen
Low Latency Real-Time Deflagration Detection Using a Field Programmable Gate Array
AUBE`21/SUPDET 2021, Conference

2020

M. Eckert, J. Haase, B. Klauer
Unifying Timer and Interrupt Management for an ARM-RISC-V-Heterogeneous Multi-Core
IECON20

2019

Timmermann, A. Klemd, D. Sachau, B. Klauer
Validation and Perfomance Analysis of a Parameterizable Mormalized Feedbeck FxLMS
Architecture for FPGA Platforms, INTERNOISE 2020

M. Eckert, D. Meyer, B. Klauer
Contrext Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs
RecoSoc 2019

A. Klemd, M. Eckert, B. Klauer, Hanselka, D. Sachau
A Parameterizable Feedbeck FxLMS
Architecture for FPGS Platforms, HEART 2019

2018

Hanselka, A. Klemd, D. Sachau, B. Klauer
Experimental results of the effect in increased filder length and sample rate of a feedback active noise control system with the FxLMS-algorithm implemented in VHDL
INTER-NOISE

M. Eckert, B. Klauer, U. Zölzer, Benois, Nowak
Low-Latency FIR Filter Structures Targeting FPGA Platforms

Proceedings of the 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART

2017

M. Eckert, D. Meyer, B. Klauer, J. Haase
Comparison and evaluation of cache parameters for softcores on FPGAs

International Conference on FPGA Reconfiguration for General-Purpose Computing, PFGA4GPC

D. Meyer, J. Haase, M. Eckert, B. Klauer
New attack vectors for building automation and IoT
IECON 2017 – 43rd Annual Conference of the IEE Industrial Electronics Society

B. Klauer, J. Haase, D. Meyer, M. Eckert
Wireless sensor/actuator device configuration by NFC with secure key exchange

IEEE AFRICON

2016

J. Haase, D. Meyer, M. Eckert, B. Klauer
Wireless sensor/actuator device configuration by NFC
IEEE International Conference on Industrial Technology (ICIT) Taipei, Taiwan

D. Meyer, J. Haase, M. Eckert, J. Klauer
Generic Operating-System-Support for FPGSs
International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany

D. Meyer, J. Haase, M. Eckert, B. Klauer
A Threat-Model for Building and Home Automation
IEEE 14th International Conference on Industrial Informatics (INDIN), France

M. Eckert, J. Haase, D. Meyer, B. Klauer
Architectural Requirements for Constructing Hardware Supported Sandboxes
International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany

D. Meyer, J. Haase, M. Eckert, B. Klauer
CloudSynth – outsourcing hardware synthesis into the cloud
Proceedings of the 42st Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy

D. Meyer, J. Haase, M. Eckert, B. Klauer
Digital Hardware Synthesis as a Cloud Service
Forum on Specification and Design Languages (FDL), Bremen, Germany

M. Eckert, D. Meyer, J.. Haase, B. Klauer
Operating System Concepts for Reconfigurable Computing: Review and Survey
International Journal of Reconfigurable Computing

M. Eckert, J. Haase, D. Meyer, B. Klauer
System Virtual Machines in the Context of Reconfigurable Computing
Proceedings of 5th Intl. Conference on Advances in Computing, Control and Networking (ACCN), Bangkok, Thailand, September 2016

2015

D. Meyer
Multicore Reconfiguration Platform – A Research and Evaluation FPGA Framework for Runtime Reconfigurable Systems
PhD Thesis, Helmut-Schmidt-University Hamburg, Hamburg

D. Meyer, J. Haase, M. Eckert, B. Klauer
Clock Speed Optimization of Partial Runtime Reconfigurable Systems by Signal Latency Measurement
Proceedings of the 41st Annual Conference of the IEEE Industrial Electronics Society, Yokohama, Japan

2014

B. Klauer
Infizierbare Hardware
Mitteilungen der Mathematischen Gesellschaft in Hamburg
Band XXXIV, 2014, ISSN 0340-4358, S. 11-20

M. Eckert
FPGA-Based System Virtual Machines
PhD Thesis, Helmut-Schmidt-University Hamburg, Holstenhofweg 85, 22043 Hamburg

2014

J. Haase, D. Meyer, M. Eckert
Towards Smart Building Automation for Private Homes
Erste transdisziplinäre Konferenz zum Thema „Technische Unterstützungssysteme, die die Menschen wirklich wollen“, Hamburg, Germany, December 2014

2013

B. Klauer
The Convey Hybrid-Core Architecture
High-Performance Computing Using FPGAs, Editors: Wim Vanderbauwhede and Khaled Benkrid, Springer, May 2013, Pages 431-451
Hardcover: ISBN 978-1-4614-1790-3
e-book: ISBN 978-1-4614-1791-0          

M. Eckert, I. Podebrad, B. Klauer
Hardware Based Security Enhanced Direct Memory Access
Communications and Multimedia Security, Editors: De Decker, Bart and Dittmann, Jana and Kraetzer, Christian and Vielhauer, Claus
Lecture Notes in Computer Science Vol. 8099, 2013, Pages 145-151, Softcover: ISBN 978-3-642-40779-6   


B. Klauer
Chap: The Convey Hybrid-Core Architecture, Book: High-Performance Computing Using FPGAs
Editor: Vanderbauwhede, Wim AND Benkrid, Khaled, Springer Science & Business Media

D. Meyer, M. Eckert, B. Klauer
CEB approach reduces the granularity problem of Runtime Reconfigurable System Design Flows
Proceedings of the Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Edinburgh, Scotland

2011

D. Wippig, B. Klauer
GPU-based translation-invariant 2d discrete wavelet transform for image processing
International Journal of Computers Issue 2 Vol. 5, NAUN

D. Meyer, B. Klauer
Multicore reconfiguration platform an alternative to RAMPSoC
SIGARCH Comput. Archit. News Issue 4 Vol. 39, ACM

2010

D. Wippig, B. Klauer
Translation-Invariant Two-Dimensional Discrete Wavelet Transform on Graphics Processing Units, Advances in Communications, Computers, Systems, Circuits and Devices, pp. 105-110, WSEAS Press, 2010        

2009         

M. Meierhöfer, B. Klauer  
TBCA – Eine Thread-basierte Cluster-Architektur
22. PARS-Workshop, Juni 2009, Parsberg in der Oberpfalz.         

2007      

M. Meierhöfer, B. Klauer
Effiziente Verteilung von Threads in Cluster-Systemen
3. Workshop Grid-Technologie für den Entwurf technischer Systeme, Dresden, Okt 2007.         

M. Schelske, M. Meierhöfer, B. Klauer
Untersuchung der Laufzeit Thread-basierter Programme auf Single- und Multicoresystemen
3. Workshop Grid-Technologie für den Entwurf technischer Systeme, Dresden, Okt 2007.         

2006         

D. Wippig, B. Klauer, H. Ch. Zeidler
Unsupervised Segmentation of Naval Infrared Images through a Markov Random Field Model
in Proc. of The 2006 Int. Conf. on Image Proc., Computer Vision & Pattern Recog. – IPCV ’06, pp. 474-489, Las Vegas, USA, Jun 2006.         

D. Wippig, B. Klauer, O. Seidel, H. Ch. Zeidler
Removing the Horizon in the Edge Representation of Infrared Images
in Proc. of the ASEE Mid-Atlantic Section Spring 2006 Conference, 28.-29.04.2006, New York, USA.          

D. Wippig, B. Klauer, H. Ch. Zeidler   
Denoising of Infrared Images by Wavelet Thresholding           
K. Elleithy et al. (eds.): Advances in Computer, Information, and Systems Sciences, and Engineering – Proceedings of IETA 2005, TeNe 2005 and EIAE 2005, S. 103-108, Springer, Dordrecht, 2006         

2005

D. Wippig, B. Klauer, H. Ch. Zeidler
Extraction of Ship Silhouettes Using Active Contours from Infrared Images
in Proc. of the 2005 Inter. Conference on Computer Vision – Vision ’05, pp. 172-177, Jun. 2005.       


HSU

Letzte Änderung: 25. November 2021