{"id":858,"date":"2018-01-15T12:41:41","date_gmt":"2018-01-15T11:41:41","guid":{"rendered":"https:\/\/www.hsu-hh.de\/ti\/?page_id=858"},"modified":"2024-02-01T16:06:27","modified_gmt":"2024-02-01T15:06:27","slug":"forschung","status":"publish","type":"page","link":"https:\/\/www.hsu-hh.de\/ti\/forschung","title":{"rendered":"Ver\u00f6ffentlichungen"},"content":{"rendered":"\n

2021<\/strong><\/h2>\n\n\n\n

A. Klemd, P. Nowak, P. Benois, E. Gerat, B. Klauer, U. Z\u00f6lzer<\/em>
Exponential Sine Sweep Measurement Implementation Targeting FPGA Platforms<\/strong>
International Conference on Field-Programmable Technology (FPT`21); Conference<\/p>\n\n\n\n

C. Sander, D. Meyer, B. Klauer<\/em>
A Survey of C++ based Agent Software Frameworks<\/strong>
International Conference on Electrical, Computer and Energy Technologies (ICECET`21); Conference<\/p>\n\n\n\n

A. Klemd, J. Timmermann, B. Klauer, D. Sachau<\/em>
A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms<\/strong>
International Conference on Field-Programmable Logic and Applications (FPL`21); Conference<\/p>\n\n\n\n

D. Meyer, J. Haase, M. Eckert, B. Klauer<\/em>
A Modern Approach to Application Specific Processors for Improving the Security of Embedded Devices<\/strong>
\u00a0IECON 2021-47rd Annual Conference of the IEEE Industrial Electronics Society<\/p>\n\n\n\n

M. Eckert, J. Kroo\u00df, B. Klauer, A. Fay F. K\u00fcmmerlen<\/em>
Low Latency Real-Time Deflagration Detection Using a Field Programmable Gate Array<\/strong>
AUBE`21\/SUPDET 2021, Conference<\/p>\n\n\n\n

2020<\/strong><\/h2>\n\n\n\n

M. Eckert, J. Haase, B. Klauer<\/em>
Unifying Timer and Interrupt Management for an ARM-RISC-V-Heterogeneous Multi-Core<\/strong>
IECON20<\/p>\n\n\n\n

D. Meyer
Applying Memristor Technology in Reconfigurable Hardware<\/strong>
Eurolab4HPC Long-Term Vision on High-Performance Computing (2nd Edition)
<\/p>\n\n\n\n

2019<\/strong><\/h2>\n\n\n\n

Timmermann, A. Klemd, D. Sachau, B. Klauer<\/em>
Validation and Perfomance Analysis of a Parameterizable Mormalized Feedbeck FxLMS<\/strong>
Architecture for FPGA Platforms, INTERNOISE 2020<\/p>\n\n\n\n

M. Eckert, D. Meyer, B. Klauer<\/em>
Contrext Save and Restore of Partial Reconfiguration Regions for Xilinx FPGAs<\/strong>
RecoSoc 2019<\/p>\n\n\n\n

D. Meyer, M.Eckert, B. Klauer<\/em>
HDL FSM Code Generation Using a MIPS-based Assembler<\/strong>
2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)<\/p>\n\n\n\n

A. Klemd, M. Eckert, B. Klauer, Hanselka, D. Sachau<\/em>
A Parameterizable Feedbeck FxLMS <\/strong>
Architecture for FPGS Platforms, HEART 2019<\/p>\n\n\n\n

D. Meyer<\/em>
Non-Volatile Processors<\/strong><\/strong>
Whitepaper: Implications of Memristor Technologies for Future Computing Systems<\/p>\n\n\n\n

D. Meyer<\/em>
Applying Memristor Technology in Reconfigurable Hardware<\/strong><\/strong><\/strong>
Whitepaper: Implications of Memristor Technologies for Future Computing Systems<\/p>\n\n\n\n

2018<\/strong><\/h2>\n\n\n\n

Hanselka, A. Klemd, D. Sachau, B. Klauer<\/em>
Experimental results of the effect in increased filder length and sample rate of a feedback active noise control system with the FxLMS-algorithm implemented in VHDL<\/strong>
INTER-NOISE<\/p>\n\n\n\n

M. Eckert, B. Klauer, U. Z\u00f6lzer, Benois, Nowak<\/em>
Low-Latency FIR Filter Structures Targeting FPGA Platforms<\/strong>
Proceedings of the 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART<\/p>\n\n\n\n

2017<\/strong><\/h2>\n\n\n\n

M. Eckert, D. Meyer, B. Klauer, J. Haase<\/em>
Comparison and evaluation of cache parameters for softcores on FPGAs<\/strong>
International Conference on FPGA Reconfiguration for General-Purpose Computing, PFGA4GPC<\/p>\n\n\n\n

D. Meyer, J. Haase, M. Eckert, B. Klauer<\/em>
New attack vectors for building automation and IoT<\/strong>
IECON 2017 – 43rd Annual Conference of the IEE Industrial Electronics Society<\/p>\n\n\n\n

B<\/em>. Klauer, J. Haase, D. Meyer, M. Eckert<\/em>
Wireless sensor\/actuator device configuration by NFC with secure key exchange<\/strong>
IEEE AFRICON<\/p>\n\n\n\n

2016<\/strong><\/h2>\n\n\n\n

J. Haase, D. Meyer, M. Eckert, B. Klauer<\/em>
Wireless sensor\/actuator device configuration by NFC<\/strong>
IEEE International Conference on Industrial Technology (ICIT) Taipei, Taiwan <\/p>\n\n\n\n

D. Meyer, J. Haase, M. Eckert, J. Klauer<\/em>
Generic Operating-System-Support for FPGSs<\/strong>
International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany<\/p>\n\n\n\n

D. Meyer, J. Haase, M. Eckert, B. Klauer<\/em>
A Threat-Model for Building and Home Automation<\/strong>
IEEE 14th International Conference on Industrial Informatics (INDIN), France<\/p>\n\n\n\n

M. Eckert, J. Haase, D. Meyer, B. Klauer<\/em>
Architectural Requirements for Constructing Hardware Supported Sandboxes<\/strong>
International Conference on FPGA Reconfiguration for General-Purpose Computing, Hamburg, Germany<\/p>\n\n\n\n

D. Meyer, J. Haase, M. Eckert, B. Klauer<\/em>
CloudSynth – outsourcing hardware synthesis into the cloud<\/strong>
Proceedings of the 42st Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy<\/p>\n\n\n\n

D. Meyer, J. Haase, M. Eckert, B. Klauer<\/em>
Digital Hardware Synthesis as a Cloud Service<\/strong>
Forum on Specification and Design Languages (FDL), Bremen, Germany<\/p>\n\n\n\n

M. Eckert, D. Meyer, J.. Haase, B. Klauer<\/em>
Operating System Concepts for Reconfigurable Computing: Review and Survey<\/strong>
International Journal of Reconfigurable Computing<\/p>\n\n\n\n

M. Eckert, J. Haase, D. Meyer, B. Klauer<\/em>
System Virtual Machines in the Context of Reconfigurable Computing<\/strong>
Proceedings of 5th Intl. Conference on Advances in Computing, Control and Networking (ACCN), Bangkok, Thailand, September 2016<\/p>\n\n\n\n

2015<\/strong> <\/h2>\n\n\n\n

D.<\/em> Meyer <\/em>
Multicore Reconfiguration Platform – A Research and Evaluation FPGA Framework for Runtime Reconfigurable Systems<\/strong>
PhD Thesis, Helmut-Schmidt-University Hamburg, Hamburg<\/p>\n\n\n\n

D.<\/em> Meyer, J. Haase, M. Eckert, B. Klauer<\/em>
Clock Speed Optimization of Partial Runtime Reconfigurable Systems by Signal Latency Measurement<\/strong>
Proceedings of the 41st Annual Conference of the IEEE Industrial Electronics Society, Yokohama, Japan<\/p>\n\n\n\n

2014<\/strong><\/h2>\n\n\n\n

B. Klauer<\/em>
Infizierbare Hardware<\/strong>
Mitteilungen der Mathematischen Gesellschaft in Hamburg
Band XXXIV, 2014, ISSN 0340-4358, S. 11-20<\/p>\n\n\n\n

M. Eckert <\/em>
FPGA-Based System Virtual Machines<\/strong>
PhD Thesis, Helmut-Schmidt-University Hamburg, Holstenhofweg 85, 22043 Hamburg<\/p>\n\n\n\n

2014<\/strong><\/h2>\n\n\n\n

J. Haase, D. Meyer, M. Eckert<\/em>
Towards Smart Building Automation for Private Homes<\/strong>
Erste transdisziplin\u00e4re Konferenz zum Thema „Technische Unterst\u00fctzungssysteme, die die Menschen wirklich wollen“, Hamburg, Germany, December 2014<\/p>\n\n\n\n

2013<\/strong><\/h2>\n\n\n\n

B. Klauer<\/em>
The Convey Hybrid-Core Architecture<\/strong>
High-Performance Computing Using FPGAs, Editors: Wim Vanderbauwhede and Khaled Benkrid, Springer, May 2013, Pages 431-451
Hardcover: ISBN<\/abbr> 978-1-4614-1790-3
e-book: ISBN<\/abbr> 978-1-4614-1791-0          <\/p>\n\n\n\n

M. Eckert, I. Podebrad, B. Klauer<\/em>
Hardware Based Security Enhanced Direct Memory Access<\/strong>
Communications and Multimedia Security, Editors: De Decker, Bart and Dittmann, Jana and Kraetzer, Christian and Vielhauer, Claus
Lecture Notes in Computer Science Vol. 8099, 2013, Pages 145-151, Softcover: ISBN<\/abbr> 978-3-642-40779-6   <\/p>\n\n\n\n


B. Klauer <\/em>
Chap: The Convey Hybrid-Core Architecture, Book: High-Performance Computing Using FPGAs<\/strong>
Editor: Vanderbauwhede, Wim AND Benkrid, Khaled, Springer Science & Business Media<\/p>\n\n\n\n

D. Meyer, M. Eckert, B. Klauer<\/em>
CEB approach reduces the granularity problem of Runtime Reconfigurable System Design Flows
<\/strong>Proceedings of the Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Edinburgh, Scotland<\/p>\n\n\n\n

2011<\/strong><\/h2>\n\n\n\n

D. Wippig, B. Klauer<\/em>
GPU-based translation-invariant 2d discrete wavelet transform for image processing<\/strong>
International Journal of Computers Issue 2 Vol. 5, NAUN<\/p>\n\n\n\n

D. Meyer, B. Klauer<\/em>
Multicore reconfiguration platform an alternative to RAMPSoC<\/strong>
SIGARCH Comput. Archit. News Issue 4 Vol. 39, ACM<\/p>\n\n\n\n

2010<\/strong><\/h2>\n\n\n\n

D. Wippig, B. Klauer<\/em>
Translation-Invariant Two-Dimensional Discrete Wavelet Transform on Graphics Processing Units<\/strong>, Advances in Communications, Computers, Systems, Circuits and Devices, pp. 105-110, WSEAS Press, 2010        <\/p>\n\n\n\n

2009<\/strong>         <\/h2>\n\n\n\n

M. Meierh\u00f6fer, B. Klauer  <\/em>
TBCA – Eine Thread-basierte Cluster-Architektur<\/strong>
22. PARS-Workshop, Juni 2009, Parsberg in der Oberpfalz.         <\/p>\n\n\n\n

2007<\/strong>      <\/h2>\n\n\n\n

M. Meierh\u00f6fer, B. Klauer<\/em>
Effiziente Verteilung von Threads in Cluster-Systemen<\/strong>
3. Workshop Grid-Technologie f\u00fcr den Entwurf technischer Systeme, Dresden, Okt 2007.         <\/p>\n\n\n\n

M. Schelske, M. Meierh\u00f6fer, B. Klauer
Untersuchung der Laufzeit Thread-basierter Programme auf Single- und Multicoresystemen<\/strong>
3. Workshop Grid-Technologie f\u00fcr den Entwurf technischer Systeme, Dresden, Okt 2007.         <\/p>\n\n\n\n

2006<\/strong>         <\/h2>\n\n\n\n

D. Wippig, B. Klauer, H. Ch. Zeidler<\/em>
Unsupervised Segmentation of Naval Infrared Images through a Markov Random Field Model<\/strong>
in Proc. of The 2006 Int. Conf. on Image Proc., Computer Vision & Pattern Recog. – IPCV ’06, pp. 474-489, Las Vegas, USA, Jun 2006.          <\/p>\n\n\n\n

D. Wippig, B. Klauer, O. Seidel, H. Ch. Zeidler<\/em>
Removing the Horizon in the Edge Representation of Infrared Images<\/strong>
in Proc. of the ASEE Mid-Atlantic Section Spring 2006 Conference, 28.-29.04.2006, New York, USA.          <\/p>\n\n\n\n

D. Wippig, B. Klauer, H. Ch. Zeidler <\/em>  
Denoising of Infrared Images by Wavelet Thresholding      <\/strong>     
K. Elleithy et al. (eds.): Advances in Computer, Information, and Systems Sciences, and Engineering – Proceedings of IETA 2005, TeNe 2005 and EIAE 2005, S. 103-108, Springer, Dordrecht, 2006         <\/p>\n\n\n\n

2005<\/strong><\/h2>\n\n\n\n

D. Wippig, B. Klauer, H. Ch. Zeidler<\/em>
Extraction of Ship Silhouettes Using Active Contours from Infrared Images<\/strong>
in Proc. of the 2005 Inter. Conference on Computer Vision – Vision ’05, pp. 172-177, Jun. 2005.       <\/p>\n\n\n\n


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